Virtual-memory multiprocessor system for parallel purge operation

ABSTRACT

A virtual memory control multiprocessor system has a plurality of processors each having a translation lookaside buffer (TLB). A purge request source processor commonly supplies a purge request signal to other processors so as to cause them to perform TLB purge operations. A purge end signal sent back from other processors is stored in flip-flops in the source processor in units of processors. The source processor detects the end of TLB purge operations of all processors, in accordance with the statuses of the flip-flops.

BACKGROUND OF THE INVENTION

The present invention relates to a virtual memory control multiprocessorsystem having a plurality of processors.

In a conventional virtual memory control multiprocessor system of thistype, a translation lookaside buffer (to be referred to as a TLBhereinafter) is arranged for each processor to perform addresstranslation from a logical address to a real address at high speed. In asystem of this type, purge (initialization) of TLBs of all processorsmust often be performed to equalize the contents of the TLBs.

As shown in FIG. 1, in a multiprocessor system having processors 10₀through 10₃, assume that the processor 10₀ supplies a TLB purge requestto the processors 10₁ through 10₃. For this purpose, the processor 10₀supplies a purge request signal la to the processor 10₃. The processor10₃ performs TLB purge processing in response to the signal 1a. In thiscase, the processor 10₀ performs its own TLB purge processing while theprocessor 10₃ performs TLB purge processing. When TLB purge processingof the processor 10₃ is completed, the processor 10₃ sends back a purgeend signal 2a to the processor 10₀. When the processor 10₀ receives thesignal 2a from the processor 10₃, the processor 10₀ sends a purgerequest signal 1b to the processor 10₂. The processor 10₂ performs TLBpurge processing in response to the signal 1b and sends back a purge endsignal 2b to the processor 10₀. When the processor 10₀ receives thesignal 2b from the processor 10₂, the processor 10₀ then sends a purgerequest signal 1c to the next processor 10₁. The processor 10₁ performsTLB purge processing in response to the signal 1c and sends back a purgeend signal 2c to the processor 10₀. When the processor 10₀ receives thesignal 2c from the processor 10₁, the processor 10₀ determines that allTLB purge operations of the processors 10₀ through 10₃ are completed.

In the conventional multiprocessor system described above, the TLB purgeoperations of the processors are sequentially performed. Assume that thetime required for a given processor to receive a purge request signal,perform purge processing in response to this signal, and send back apurge end signal to the processor which has supplied the purge requestsignal thereto is defined as T. In this case, in the system of FIG. 1,the total time for all the TLB purge operations of the four processors10₀ through 10₃ is 3T, as shown in FIG. 2. In a multiprocessor forsequentially performing TLB purge operations, TLB purge time is linearlyincreased in proportion to the number of processors, resulting ininconvenience.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a multiprocessorsystem wherein the total purge time for translation lookaside buffers,with respect to the total processing time of the entire system, can beshortened.

According to the multiprocessor system of the present invention, all theprocessors including a purge request source processor can performparallel purge operations. In addition, the end of the purge operationof each processor can be set by a corresponding flip-flop. By checkingthe statuses of the flip-flops, the end of the purge operations of allthe processors can be detected. Therefore, the time for purge operationscan be greatly shortened.

In order to achieve the above object of the present invention, there isprovided a virtual memory control multiprocessor system having aplurality of processors each having a translation lookaside buffer,including:

purge request signal generating means for supplying a common purgerequest signal requesting purge operations of translation lookasidebuffers of other processors excluding a source processor for generatingthe common purge request signal which is supplied in parallel to theother processors;

a plurality of flip-flops for storing, in units of processors, a purgeend signal sent back from the other processors which complete purgeoperations in response to the common purge request signal generated fromthe purge request signal generating means; and

purge end detecting means for checking the statuses of the plurality offlip-flops and detecting the end of purge operations of all processors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a conventional multiprocessorsystem;

FIGS. 2A through 2B are respectively timing charts for explaining TLBpurge operations of all processors shown in FIG. 1;

FIG. 3 is a schematic block diagram of a multiprocessor system to whichthe present invention is applied;

FIG. 4 is a circuit diagram of a circuit of the processor system (FIG.3) which is directly associated with the present invention; and

FIGS. 5A through 5D are respectively timing charts for explaining TLBpurge operations of the processors shown in FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 3 shows a virtual memory control multiprocessor system according toan embodiment of the present invention. Referring to FIG. 3, processors20₀ through 20₃ have translation lookaside buffers (TLBs), respectively.The processors 20₀ through 20₃ are connected to each other through asystem bus 21. The processors 20₀ through 20₃ receive and send a purgerequest signal a through a signal line 22 and a purge end signal bthrough a signal line 23. The lines 22 and 23 shown in FIG. 3 constitutepart of the system bus but are separately illustrated for descriptiveconvenience.

FIG. 4 shows an arrangement of the processor 20_(i) (i=0 through 3) ofFIG. 3 which is directly associated with the present invention. A busdriver 31 sends the signal a onto the line 22. A bus receiver 32receives the signal a from the line 22. A bus driver 33 sends the signalb onto the line 23. A bus receiver 34 receives the signal b from theline 23. A bus driver 35 sends a processor number including an addressto an address bus of the bus 21. A bus receiver 36 receives address datafrom the address bus of the bus 21. The address data comprises, forexample, a processor number, a command and auxiliary data. The signal bis included in the command.

A decoder 37 decodes a predetermined field (i.e., processor number) ofthe address fetched by the receiver 36. Decode signal lines 38₀ through38₃ correspond to processor numbers of the processors 20₀ through 20₃,respectively. Each of the lines 38₀ through 38₃ is connected to oneinput terminal of a corresponding one of 2-input NAND gates 39₀ through39₃. The signal b is supplied to the other input terminal of each of theNAND gates 39₀ through 39₃ through the receiver 34. Output signals fromthe NAND gates 39₀ through 39₃ are supplied to set input terminals S ofR-S flip-flops 40₀ through 40₃, respectively. A signal 41 is supplied toa reset input terminal R of each flip-flop 40_(i) (i=0 through 3) toreset it. Q outputs from the flip-flops 40_(i) are supplied to 3-inputOR gates 42₀ through 42₃, respectively. The OR gates 42₀ through 42₃also receive signals 47₀ through 47₃ representing that the processorsgenerating the signals a are the processors 20₀ through 20₃ and signals48₀ through 48₃ representing that the processors 20₀ through 20₃ are notpresent. Outputs from the OR gates 42₀ through 42₃ are supplied to a4-input AND gate 43. An output signal 45 from the AND gate 43 is used asthe purge end signal which is received by the processor which hasgenerated the signal a.

The operation of the multiprocessor system of this embodiment will beexemplified wherein the processor 20₀ sends the TLB purge request signala to the remaining processors 20₁ through 20₃, as shown in FIG. 3, withreference to the timing charts of FIGS. 5A through 5D.

The processor 20₀ supplies the signal a onto the line 22 through thedriver 31 in the processor 20₀. The signal a on the line 22 is commonlysupplied to the processors 20₁ through 20₃ and is fetched therebythrough the corresponding bus receivers 32 in the processors 20₁ through20₃. The TLB purge operations are simultaneously performed in responseto the signal a commonly fetched by the processors 20₁ through 20₃, asshown in FIGS. 5A through 5D. The TLB purge operation of the sourceprocessor 20₀ is also performed while the processors 20₁ through 20₃perform the corresponding TLB purge operations after the processor 20₀sends the signal a thereto.

When the processors 20₁ through 20₃ complete the TLB purge operations,they send back the signals b onto the line 23 through the correspondingbus drivers 33 if the bus 21 is available. In this case, the processors20₁ through 20₃ send their own processor numbers onto the address bus ofthe bus 21 through the corresponding bus drivers 35. The processornumber data on the system bus 21 are supplied to the decoder 37 in thesource processor 20₀. The decoder 37 decodes the processor numberssupplied through the receivers 36. When the processor number datasupplied to the decoder 37 of the processor 20₀ represents that from theprocessor 20₁, the decoder 37 sends an active signal of logic "1" ontothe signal line 38₁. This signal is supplied to one input terminal ofthe NAND gate 39₁. The other input terminal of the NAND gate 39₁receives the signal b sent from the processor 20₁ through the line 23and the corresponding receiver 34. The NAND logic of the NAND gate 39₁in the processor 20₀ is established, and an output signal therefrom goesfrom logic "1" to logic "0". This transition indicates that the signal bfrom the processor 20₁ is detected by the NAND gate 39₁.

The output signal from the NAND gate 39₁ is supplied to the set terminalS of the flip-flop 40₁. The flip-flop 40₁ is set when the output signalfrom the NAND gate 39₁ is inverted from logic "1" to logic "0" and theset input terminal of the flip-flop 40₁ is inverted from logic "0" tologic "1". In other words, the flip-flop 40_(i) stores the purge endsignal sent from the processor 20₁. The above operation can also beapplied when the signals b and the corresponding processor numbers aresent from the processors 20₂ and 20₃. More particularly, when theprocessor 20₂ supplies the signal b and its own processor number to theprocessor 20₀ through the line 23 and the bus 21, the flip-flop 40₂ inthe source processor 20₀ is set. Similarly, when the processor 20₃supplies the signal b and its own processor number through the line 23and the bus 21 to the processor 20₀, the flip-flop 40.sub. 3 in thesource processor 20₀ is set.

When the flip-flops 40₁ through 40₃ are set, their Q output signals 46₁through 46₃ go from logic "0" to logic "1". The Q output signals 46₁through 46₃ are supplied to the OR gates 42₁ through 42₃, respectively.As a result, the OR gates 42₁ through 42₃ are rendered conductive, andtheir output signals 44₁ through 44₃ go from logic "0" to logic "1",respectively.

Since the processor 20₀ serves as the TLB purge request sourceprocessor, it does not generate the signal b and its own processornumber. As a result, the flip-flop 40₀ in the processor 20₀ is keptreset, and the Q output signal of logic "0" therefrom is supplied to theOR gate 42₀. Other terminals of the OR gate 42₀ receive the signal 47₀representing that the processor generating the signal a is the processor20₀ and the signal 48₀ representing that the processor 20₀ is notpresent. In this embodiment, since the processor 20₀ serves as the TLBpurge request source processor, the signal 47₀ of logic "1" is suppliedto the OR gate 42₀. As a result, the output signal 44₀ from the OR gate42₀ is set at logic "1".

The output signals 44₀ through 44₃ from the OR gates 42₀ through 42₃ aresupplied to the AND gate 43. The AND gate 43 generates a signal of logic"1" when all the signals 44₀ through 44₃ are set at logic "1". As aresult, the TLB purge request source processor 20₀ checks the outputsignal 45 from the AND gate 43. When this signal is set at logic "1",the processor 20₀ determines that all the TLB purge operations of theprocessors 20₀ through 20₃ are completed, thereby initiating the nextoperation.

The above operation can be performed when all the processors 20₀ through20₃ are present. However, when the processor 20₃ is not present, thefollowing operation is performed. The signal 48₃ representing that theprocessor 20₃ is not present is set at logic "1". The signal 48₃ oflogic "1" is supplied to the OR gate 42₃. The OR gate 42₃ supplies thedummy TLB purge end signal to the AND gate 43. If the processor 20₃ isnot present, the processor 20₀ can detect that all the TLB purgeoperations of the processors 20₀ through 20₂ are completed.

In the above embodiment, the maximum number of processors is four.However, the present invention can be applied to a multiprocessor systemhaving any number of processors.

In the above embodiment, the purge request signal transfer signal line22 and the purge end signal transfer signal line 23 are arranged.However, these signal lines can be omitted. For example, a purge requestcode corresponding to the signal a and a purge end code corresponding tothe signal b can be provided, and these code data can be transferredthrough a predetermined field of the address bus in the bus 21. In thiscase, each processor must have decoding means for decoding the purgerequest code and the purge end code.

What is claimed is:
 1. A virtual-memory-type multiprocessor systemhaving a plurality of processors each having a translation lookasidebuffer, comprising:a first processor having a purge request signalgenerating means for supplying a common purge request signal requestingpurging of translation lookaside buffers of said other processors; aplurality of flip-flops provided in each of said plurality of processorseach of said flip-flop for storing a corresponding purge end signal, foreach of said plurality of processors, each of said other processors,upon completion of purge operations in response to the common purgerequest signal, sending a corresponding processor number to each otherprocessor; each of said processors further comprising: a decoder fordecoding each processor number sent and setting the flip-flopcorresponding to the decoded processor number; and purge end detectingmeans connected to each of said plurality of flip-flops for detectingthe end of the purging of all processors.
 2. A system according to claim1, wherein said purge end detecting means comprises:first gates,respectively connected to said flip-flops, for receiving output signalstherefrom, a signal indicating said source processor, and a signalindicating absence of any one of said processors from saidmultiprocessor system, and for outputting the logical sum of all inputsignals; and a second gate connected to each of said first gates foroutputting the logical product of all the output signals from said firstgates.